1. Field of the Invention
The present invention relates to voltage controlled oscillators (VCO's), and more particularly to linearizing gain (frequency out/voltage) of VCO's over a wide frequency range.
2. Background Information
VCO's are commonly used in many applications, especially in communication and control applications. Virtually all phase-locked-loop (PLL) circuits employ a VCO in the control loop. FIG. 1 is a block diagram of such a phase-locked-loop circuit. A phase and frequency detector 2 compares an input reference or clock signal 4 to a feedback signal 6 that is a frequency divided VCO output signal 8. The phase-frequency detector 2 provides an UP or DOWN error signal into a charge pump 10 that together with a Loop filter 12 generates a control voltage Vcnt 14. A Loop Buffer 16 and a VCO 18 complete the loop to the VCO output signal 8. The feedback signal 6 is derived from signal 8, typically (but not necessarily) by dividing the signal as shown. As is well known in such systems the feed back loop operates to reduce the differences between the clock signal 4 and the divided signal 6. Not shown, but often found in such circuits, are analog to digital converters that may form parts of the PLL loop. In such cases the operations described in any one block of FIG. 1 are carried out digitally as is well known in the art.
Most VCO's used in a PLL and elsewhere strive to operate over a wide frequency range. One primary aspect determining that frequency range is the linearity of the VCO's gain. Non-linearities tend to increase phase offsets between the input and looped back signal and change the loop gain which may lead to “overshooting” and other stability issues. This in turn leads to compromising the loop filter parameters, which leads to limiting the operating frequency range of the PLL. Other negative effects of non-linearities may include increased noise, increased acquisition times, and/or frequency jitter.
FIG. 2 is a common delay string of five pulse delay elements, t1–t5, that wraps around to create an oscillator circuit. A control signal, Vcnt, is fed to each delay element to change the delay of each element and thus the frequency of the circuit. This type of oscillator is found in the prior art and may be used in a preferred embodiment of the present invention. FIG. 3 diagrams a five stage oscillator where the output of the last delay circuit, t5, loops back to the input of the first delay circuit, t1. A phase reversal is incorporated into the loop to cause oscillations. In such a circuit the delay, T, of each circuit is added to get the period P of the oscillator, and inverting the period yields the frequency. If each circuit delay is equal, the resulting frequency is an inverse function of one circuit delay, or Fosc=K1(1/T). The power on reset, POR, allows the oscillation to start.
FIG. 4 shows the optimal relationship for a VCO where the frequency out is a straight line function of a control voltage in with a slope of K2. The relationship as applied to a VCO with an input control voltage, Vcnt, is:Fosc=K2(Vcnt) plus some offset  Eq. 1
The following discussion drops the offset and considers the relationship to pass through the origin for simplicity. However, as will be understood by those skilled in the art, there is no loss in the general applicability of the following discussion.
The effort to linearly extend this line has been an ongoing objective in the art and is an objective of the present invention.
It is well known in the art to use a current source to charge a capacitor to create a delay circuit suitable for use in a delay type oscillator described above. The well known relation ship of a current I charging a capacitor C is:I=C(dv/dt)  Eq. 2.The delay, T, of one delay circuit, will be a function of the time it takes the voltage on the charging capacitance to reach some circuit determined threshold level, V1. V1 is considered for this discussion to start from a complete discharge or zero volts. Again there will be some small residual voltage, that will not affect the general applicability of the present invention as understood by those skilled in the art. So the dv/dt can be written as V1/T, and Eq. 2 becomesI=C(V1/T). Rearranging yields:1/T=(I/CV1)  Eq. 3, andT=(CV1/I)                So, the delay of one circuit is CV1, and the frequency of the delay circuit will be a constant equal to the number of delay circuit stages times 1/T, orFosc=K1(1/T)=K1(I/CV1).As discussed below the current, I, of Eq. 3 is shown to be a function of the square of Vcnt (Vcnt^2) for a specific design, and so, as discussed above, the frequency of the sequential delay circuit oscillator will be:Fosc=(K3/CV1)Vcnt^2  Eq. 4        
As discussed below, V1 is a function of Vcnt, and C is a constant along with K3, resulting in:Fosc=(K3/C)(Vcnt^2/Vcnt)  Eq. 5, orFosc=K2(Vcnt),  Eq. 6,
which is a relationship oF interest as discussed below.
FIG. 5 is a copy of item 22 from U.S. Pat. No. 5,748,048 to Moyal (Moyal), and assigned to Cypress Semiconductor Corp. Moyal and FIG. 6 completes a partial schematic showing a single delay stage of charging of the capacitor C that illustrates the square law relationship. In FIG. 5, P3 and N2 are operated as FET diode clamps. A FET diode clamp is a FET that operates in the saturation region where the drain current is approximately related to the square of the gate to source voltage. Here the current I1 is proportional to the square of the Vcnt (less threshold voltages). Current I1′ mirrors I1, and, following FIG. 6, I1″ mirrors I1′ (although with current mirrors there may be a factor due to channel size involved). The delay of I1″ charging capacitor C is inversely related to I1,″ as is well known. As applied to the analysis above, from FIG. 5 and Eq. 4, Vcnt will be related to the root of I1 and therefor to maintain the linearity of FIG. 4. The V1 of Eq. 4 will also be related to the square root of I, therefore canceling each other out of Eq. 4 as shown above in Eq. 5.
It is clear that linear frequency range shown in FIG. 4 depends on the square law relationship discussed above. Moreover, to extend the linear relationship of FIG. 4, the square law relationship, Vcnt to I1, of FIG. 5 and Eq. 4, must be correspondingly extended.
In the circuit of FIG. 5, since P3 and N2 are FETS built simultaneously with N1, P1 and the other FETS, process variations from chip to chip or batch to batch will correlate among the FETs. For example the temperature coefficients, TC's (usually positive) will track and at higher temperature larger FET threshold voltages, Vt's, will act to restrict the operating range of the circuit. In this case “threshold” refers to the gate voltage necessary to drive a given drain current, not the threshold that begins to turn on an FET. Moreover, if the fabricating process produces slow FET's, all will be slow and may affect the high frequency range of the VCO. Also, as the Vcnt goes low, the threshold of the FET's become a factor and the square law relationship may not hold. In such a case the linearity of the VCO will deteriorate causing problems discussed above.
The present invention addresses these limitations.